SE From GAA To CFET: Scaling Transistors For The AI Era

Post by **admin** » Thu Aug 27, 2026 7:03 am

By Urmimala Roy, Xi-Wei Lin, and Ravi Todi Two years ago, we introduced why the industry was moving to gate‑all‑around (GAA) transistors and why Foundation IP co-optimized with electronic design automation (EDA) flows would be key to success to making that transition work. Since then, GAA has moved from early adoption into the mainstream of leading-edge design—and the industry’s attention is already turning to what comes next. As designs push past the 2nm node, the architectures that carried CMOS scaling for decades are reaching their practical limits, and the demands of AI computing are adding to the pressure. Each new node must deliver better power, performance, and area (PPA) while managing new physical realities, from quantized device widths and weakening electrostatic control to the thermal challenges of backside power delivery. Increasingly, meeting those targets depends not on the transistor alone, but on how closely Foundation IP and EDA flows are co-optimized for the target process. This article revisits where GAA stands today and the two key enablers, backside power delivery and design-technology co-optimization (DTCO), that help realize its full benefit. It then looks ahead to GAA’s successor, the complementary FET (CFET), which two years ago was on the horizon and today has moved from concept to demonstrated silicon. GAA today: Where the technology stands Beginning at around the 2nm node, the industry started transitioning to a new transistor architecture, gate-all-around (GAA). In GAA, there are nanosheets of semiconductors with the gate wrapping around them on all four sides (Figure 1), which lets the gate voltage control the charge in the channel more effectively than a FinFET.

Fig. 1: Cross-section showing nanosheets stacked as in a GAA transistor. You can see the gate’s stronger grip in a steeper sub-threshold slope (SS), which translates to a higher Ion/Ioff ratio (a transistor, as a switch, will carry the current Ion in its “on” state and the current Ioff, when in the “off” state). GAA offers better electrostatic control and hence the steeper SS. Another advantage of GAA is that the channel thickness is better controlled in the manufacturing process, leading to smaller device variations. GAA can also be thought of as fins flipped sideways and then stacked vertically. That makes the width continuous in the plane of the layout [3], allowing the process to be optimized using the nanosheet width as a variable. In effect, nanosheet width becomes a knob designers can turn to balance performance against area (Figure 2). Wide transistors help achieve high performance in a standard cell owing to higher current carrying capability, which makes high-performance standard cells ideal for high-performance computing. Conversely, narrow transistor width can be used for high-density, low-power standard cells, which are better suited to battery-powered mobile applications [3]. It’s worth noting that planar, FinFET, and GAA devices are each likely to keep playing a role: not every system-on-chip (SoC) function needs to be implemented in the most advanced node, and heterogeneous, multi‑die designs increasingly bring these transistor types together in a single product.

Fig. 2: Standard cell representational top view (not to scale). GAA allows flexible transistor width. Why GAA is critical in the AI era An important implication of transistor scaling is that each subsequent node consumes less power than its predecessors. Right now, the semiconductor industry’s growth is fueled by the artificial intelligence (AI) “revolution”. With the introduction of large language models to a broader audience in 2022, the user base of AI tools has grown exponentially. Training such models requires a huge amount of computation, which, in turn, needs specialized hardware such as GPUs, often sitting in large data centers. It is predicted that, at the current rate of growth, data centers will consume ~7-8% of global electricity demand sometime around 2030 (Figure 3) [3, 4]. That kind of power draw puts real pressure on the global electricity infrastructure, and it’s a big reason the industry is so focused on designing chips that consume less power. This makes GAA (and its successor transistor geometries) particularly important in the AI era. Today, high‑performance mobile is leading GAA adoption, with hyperscale servers and high‑performance CPUs following closely behind—a clear shift from the early‑adoption picture of just two years ago.

Fig. 3: Current and future forecasts on global electricity demand due to data centers [3]. Two enablers: Backside power and DTCO Two architectural shifts are enabling GAA’s full potential at advanced nodes:

Backside power delivery: Traditionally, the transistors are built first, then many layers of metal are stacked on top to route power and signals between them. As dimensions shrank, routing became harder, with signal and power competing for space. In recent years, foundries have begun separating power and signal delivery to the transistor from two opposite sides of the transistor layer. This frees up more space for both and makes routing easier. With backside power delivery, bulk silicon no longer sitting beneath the transistors to carry heat away, so self-heating becomes a challenge to manage.
Design technology co-optimization (DTCO): Standard cells and static random-access memories (SRAMs) take up most of the area inside a SoC [5], so they largely determine its power, performance, and area (PPA). Beyond reducing the dimensions that impact cell area—such as contacted poly pitch (CPP), gate length, and metal pitch—advanced nodes require optimizing many other aspects to achieve desired PPA, including co-optimization with advanced EDA tools [5]. A technology can be optimized for PPA at multiple levels: gate length, poly pitch, and metal pitch at the first level; then gate cross-coupled structures and diffusion breaks; then optimizing for place-and-route access for the pins; and ultimately, at the block level [5].

Helping design teams make the leap Realizing these benefits in a real SoC depends on high‑quality IP and EDA flows that are co‑optimized for the target process—the same point we made two years ago, and it holds even more true today. Drawing on a 20‑year history of developing Foundation IP across the planar and FinFET eras, and on work with hundreds of customers, Synopsys 2nm GAA Foundation IP is being delivered to customers today, co‑optimized with Synopsys EDA flows to enable the most area-optimized designs, and, ultimately, the lowest total cost of ownership at advanced nodes. Synopsys’ technology computer-aided design (TCAD) tools help in technology development and DTCO by enabling simulation of electrical/thermal characteristics of transistors at the advanced node geometries, including GAA and CFET. On the EDA side for physical implementation, the Synopsys Fusion Design Platform (an integrated, golden‑signoff RTL‑to‑GDSII flow) has been qualified for GAA process technologies at major foundries. In addition, Synopsys has collaborated with foundries to optimize our AMS Design Reference Flow, based on Synopsys Custom Design Platform, for the GAA process. As the industry moves toward CFET and angstrom‑scale nodes, this same IP‑plus‑EDA co‑optimization is what will let design teams hit ever more demanding PPA targets. What’s next: The move to CFETs The unprecedented demand for semiconductor chips driven by the AI “revolution” calls for continued device scaling to enable lower power consumption, smaller chip area, and faster chips. Two years ago, we noted that CFETs were on the horizon; today they have moved from concept to demonstrated silicon. Beyond GAA, the next generation of transistors is expected to be CFETs, where the NMOS and PMOS are stacked vertically (Figure 4), shrinking footprint and increasing transistor density.

Fig. 4: 3D image showing NMOS and PMOS stacked vertically in a CFET-like arrangement. Recently, researchers demonstrated working ring oscillators and SRAM cells built with CFETs [6]. As with GAA technology, DTCO will be an important part of PPA optimization for CFETs [6]. Recent work demonstrated 3.5-track CFET designs in A7 (7 Å technology equivalent) reaching 46% area reduction compared to their N2 (2nm technology equivalent) reference, while keeping performance the same [7]. Potentially combined with backside power delivery and with the growing role of multi‑die, chiplet‑based design, CFET is poised to be the next step in extending scaling into the angstrom era. For more information, visit: Synopsys Foundation IP References

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Xi-Wei Lin is executive director of applications engineering at Synopsys. Ravi Todi is executive director of product management for Foundation IP and Security IP at Synopsys. The post From GAA To CFET: Scaling Transistors For The AI Era appeared first on Semiconductor Engineering.

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