Key Takeaways:
- Photonics changes chiplet design from a placement problem into a multi-physics co-design problem because thermal, mechanical, electromagnetic, and optical effects interact bidirectionally.
- The closer optical chiplets move to compute silicon, the more bandwidth and power improve — but the harder it becomes to manage heat, stress, alignment, and reliability.
- Chip architects should start with traffic patterns, system architecture, and verifiable interface contracts before deciding where optics belongs.
Optical chiplets promise a way out of the bandwidth, power, and reach limits of copper interconnects, but bringing photonics into advanced packages is proving more difficult than just swapping one signaling medium for another. As optical devices move closer to silicon, they become part of a tightly coupled physical system where heat, stress, electromagnetic effects, alignment, and verification all interact. As a result, photonics becomes less of a component-level choice than a system-level architecture problem that includes the die, package, interconnect, and system stack. Currently, semiconductor companies are moving photonic integrated circuits (PICs) into the same package as high-performance processors, switches, and memory dies to replace traditional copper interconnects in co-packaged optics (CPO) approaches. At the same time, commercial design-ins are picking up, with hyperscalers and major hardware developers adopting optical chiplet architectures into initial production and deployment phases for AI data centers. Dozens of specialized patents and active prototypes confirm that optical engines are shifting from research concepts to product readiness. To speed adoption, TSMC introduced Compact Universal Photonic Engine (COUPE), an open infrastructure for mass-producing optical chiplets. Instead of placing the electronic integrated circuit (EIC) and the PIC side-by-side on a substrate, TSMC stacks them vertically. The electronic control chip is stacked directly on top of the optical chiplet, connected using hybrid bonding that replaces traditional solder balls with copper-to-copper connections. TSMC says stacking the chips vertically reduces the distance signals must travel, shrinks electrical parasitic resistance to near zero, cuts data transmission power consumption by up to 85%, and optimizes server space for high-density AI clusters. The challenge is no longer whether photonics belongs in chiplet systems, but where it belongs, how close it should sit to logic, and how much of the package must be co-designed around it. The closer optics is to the processing elements, the lower the latency and the amount of energy required to move signals. But it also exposes the optical signals to thermal drift, mechanical stress, electromagnetic coupling, and verification gaps that cannot be solved one chiplet at a time. “The chip architect cannot think of it as an independent chiplet,” noted Gilles Lamant, distinguished engineer and Virtuoso platform architect at
Cadence. “And that’s even worse now that everybody is going with hybrid bonding. With hybrid bonding, you decrease the separation between the electrical chip and the photonic chip. There’s nothing in between. So the photonic chiplet is both an aggressor and a victim in that new system, and there are plenty of thermal considerations. The interposer acts as an insulator. Mechanically, solder balls had to go on these things. All of this is gone, so now you cannot really look at those two chips in isolation from a thermal perspective. That interaction is bidirectional, which many people overlook. The photonic chip generates significant heat, and heat creates problems for electronics, including faster aging. In that sense, the photonic chip can act as an aggressor toward the electronic chip. Stress also develops at the boundary between the two. Photonic devices are typically very sensitive to temperature, and designers often use thermal tuning to adjust waveguide properties. But that also means any temperature variation on the photonic side can become a problem. It’s literally bidirectional, which is why you need to design those two together.” In addition to TSMC, Intel Foundry, GlobalFoundries, STMicroelectronics, and Tower Semiconductor are manufacturing photonics chips today. In Europe, Lamant noted that ST is pursuing a hybrid bond strategy, with an EIC on top of a PIC. “The hardest issues are the ones at the system level,” Lamant noted. “It’s not magic. It’s just that the amount of data is significant and processing that data is hard.” Photonics chiplets already are shipping alongside traditional silicon chiplets. “[These are being implemented as] a heterogeneous assembly — a compute die, an EIC for SerDes, drivers and control, and a PIC for modulation and detection, co-packaged with standard interconnect,” observed Ashish Darbari, CEO of
Axiomise. “Ayar Labs’ TeraPHY offers a UCIe-compliant electrical interface and 8 Tbps of bidirectional optical bandwidth. The Alchip and Ayar Labs demonstration on TSMC’s COUPE platform delivers up to 100 Tb/s per accelerator behind a standard UCIe interface, and the UCIe Consortium, over 120 members strong, treats optical interconnect as a core vertical.” As a result, this has become a chiplet specification explosion problem with a twist for verification purposes. “One die boundary is now a physical-domain conversion,” Darbari explained. “The digital side is tractable. We formally verify chiplet protocols, and a UCIe adapter is exactly where formal methods exhaustively prove the absence of deadlock and protocol violations. The optical side behind it has no comparable discipline yet. That asymmetry, a formally verified electrical contract wrapped around an informally specified optical subsystem, should worry system architects.” So how exactly do photonics chips fit into chiplets alongside traditional silicon chips? John Ferguson, product management director for Calibre nmDRC applications at
Siemens EDA, explained that, in general, a photonic chip can be placed in the same way as any other chip within a 3D-IC assembly. “However, there does need to be careful consideration about how to convert optical signals to electrical, and vice versa, and there may be more careful planning for placement of the photonic chip to avoid signal distortion due to thermal and mechanical stresses.” According to Guillaume Boillet, vice president of strategic marketing at
Arteris, a photonic chiplet is best understood as another die in the package that happens to communicate with light instead of electrons, and in practice that link stays largely transparent to the network-on-chip as long as the die-to-die controllers on the other side speak protocols the fabric already supports. “The interesting shift for chiplet architects comes when optical is used to span longer distances than electrical signaling allows, extending the practical reach of a system and pushing multi-die designs toward larger, more distributed topologies. Further out, on-chip optical interconnect is an emerging technology worth watching, since it will require industry-wide NoC architectures to interface with it natively without degrading the latency the rest of the system depends on.” Further, in a 2.5D architecture, the compute, memory, electronic-interface, and photonic chiplets are placed side by side on a silicon interposer, organic substrate, or advanced redistribution layer. “This is the more mature, lower-risk approach as it reuses standard interposer/RDL processes, and it also allows the photonic chiplet to be reused with different compute dies,” noted photonics physicist and researcher John Bowers, a board member and advisor to
ChipAgents. “But the EIC-to-PIC electrical trace length adds parasitic capacitance and inductance that caps how fast you can drive the modulators. In a 3D implementation, the electronic interface die can be bonded directly above or below the photonic die using micro bumps, copper-to-copper hybrid bonding, or another fine-pitch interconnect technology. This shortens the electrical link between driver circuits and modulators/photodetectors to microns instead of millimeters, which is what lets designs push to higher baud rates with lower drive voltage and power per bit. This is the direction most co-packaged-optics roadmaps (Intel, TSMC COUPE, Ayar Labs, Broadcom) are heading.” Further, in a 2.5D architecture, the compute, memory, electronic-interface, and photonic chiplets are placed side by side on a silicon interposer, organic substrate, or advanced redistribution layer. “This is the more mature, lower-risk approach as it reuses standard interposer/RDL processes, and it also allows the photonic chiplet to be reused with different compute dies,” noted John Bowers, a photonics physicist and researcher and board member and advisor to
ChipAgents. “But the EIC-to-PIC electrical trace length adds parasitic capacitance and inductance that caps how fast you can drive the modulators. In a 3D implementation, the electronic interface die can be bonded directly above or below the photonic die using micro bumps, copper-to-copper hybrid bonding, or another fine-pitch interconnect technology. This shortens the electrical link between driver circuits and modulators/photodetectors to microns instead of millimeters, which is what lets designs push to higher baud rates with lower drive voltage and power per bit. This is the direction most co-packaged-optics roadmaps (Intel, TSMC COUPE, Ayar Labs, Broadcom) are heading.” This is evolving from the first generation of photonics, where the optics came in a pluggable module. “That is where electro-optical conversion happened,” said Priyank Shukla, senior director of product management at
Synopsys. “From the side view, you’d have a host chip, or it could be a switch, and there is an electrical signal through a PCB going through a pluggable module. This is what we see in deployment. However, you can implement pluggability another way without re-timing the electrical IC, since the electrical signal drives the optics directly. It’s still pluggable, but the optical drive is linear. That’s one way to save power because you don’t have additional timing delay. So from a form-factor point of view, these are still pluggable. Electrical and optical chips live far apart.” What is happening now are two stages of integration for near-packaged optics and co-packaged optics. “In near-packaged optics, an optical component comes in and is soldered on a board so your electrical domain will go through a board and drive the optics here,” Shukla explained. “Now the laser of that optical chain could still be in a pluggable module, the modulator could be near, and the driver could be in the near-packaged optics. This is the second stage of integration we are seeing. We also see some deployment clusters that value near-packaged optics. In terms of pros and cons, it’s more serviceable, but it also has design challenges, such as thermal drift. One group of engineers is interested in this deployment, and another group is considering co-packaged optics, where the laser will still be in the external small-form-factor pluggable, but other components can be co-integrated here. Then, when you co-package the optics, there are different streams. How do you integrate electrical and optical together? Do you place it on top of the edge, and do you have one versus another?” Another consideration here is that the photonic die becomes another chiplet in the package, but a distinctive one, according to Kent Orthner, vice president of products at
Baya Systems. “Where compute and memory dies process data, an optical chiplet is mostly an I/O element whose job is getting enormous bandwidth on and off the package. It attaches through standard die-to-die interfaces and PHYs like UCIe and BoW, and to the on-die network it looks like a very high-bandwidth endpoint that needs to be fed. As the industry starts to integrate optics into compute silicon, this story largely stays the same: optical devices look like bandwidth-hungry endpoints in the system, and keeping them fed becomes the challenge.” Ultimately, that heterogeneity should be invisible. “Whether an endpoint is a compute die, a memory die, or an optical I/O tile, the fabric must deliver data to it as a first-class citizen. A modular, tile-able fabric lets architects place those optical on ramps wherever the system needs them, instead of forcing the whole design around them,” Orthner said.
Thermal challenges Thermal issues with photonics chips make chiplet design more challenging. “The device-level thermal behavior, especially in silicon photonic components like ring modulators, whose resonance drifts with temperature and needs active tuning, is the domain of photonics and packaging teams, more than the design team, and what this creates for the design side is a system tension since optical-control silicon, such as the modulation circuitry, wants to sit somewhere cool and thermally stable, while the hottest thing in the package is usually the compute logic right next to it,” Orthner said. “Thermal turns interconnect placement into a co-optimization problem — high-activity switching generates heat, and you don’t want that concentrated next to thermally-sensitive silicon. A software-defined fabric helps because you can model where the fabric’s hotspots land and explore placement tradeoffs early, before you’ve committed silicon, rather than discovering a thermal conflict at the floorplan stage. We don’t tune the optics, but we can make thermal a first-class variable in the architecture exploration.” Given these challenges, does that mean optical chips might not be appropriate to include in a chiplet system? Not necessarily. “Even in an electronic circuit, thermal effects will often be the limiting factor of the system. This is why we see new packaging technologies such as glass substrates,” said Niels Faché, senior vice president at Keysight EDA. “If you can’t exceed 85 degrees Celsius, you may only be able to generate a few watts in your power amplifiers unless you remove heat. You can’t rely on natural convection alone. If you use fluids to remove heat, you can move that limit up by an order of magnitude and effectively remove thermal effects as the system’s limiting factor. In electro-optical systems, it’s the same. Thermal management is critical because you’re going to such high data rates and such dense integration that thermal effects become the limiting factor. You don’t just have to model it. You also must develop packaging technologies that remove heat in a way that lets you handle the power levels required in those systems.” ChipAgents’ Bowers explained that thermal issues with photonics chips make chiplet design more challenging for several reasons. “Silicon’s refractive index varies with temperature. As a result, temperature changes can alter optical phase and shift the center wavelength of resonant devices. A photonic circuit can remain electrically connected and fully operational yet lose optical performance because its resonances are no longer aligned with the laser wavelengths.” In a vertical stack, where an EIC is bonded directly onto the PIC, the driver/SerDes circuits dissipating watts of heat are microns away from ring resonators that must stay within a fraction of a degree of their operating point. “That’s the opposite of what you want thermally, even though it’s exactly what you want electrically (short link, low parasitics),” Bowers said. Lasers add another layer of thermal complexity. “Their efficiency, output power, wavelength, and lifetime depend on temperature. Placing lasers next to a high-power processor can increase cooling requirements and create feedback between laser wavelength and photonic-filter alignment. Temperature changes also cause the package materials to expand at different rates. Silicon, organic substrates, glass, underfill, copper, adhesives, optical fibers, and III–V materials have different coefficients of thermal expansion,” Bowers noted. “Liquid cooling may produce steep gradients or place cooling hardware near sensitive optical interfaces. The cooling solution must avoid applying excessive mechanical load to the photonic die or fiber assembly while still removing heat from the processor and laser sources. Fiber coupling and optical connector coupling depend on alignment with the photonic waveguide, and are typically temperature-dependent. But the coupling must be high across all operating states. The thermal design must therefore include the complete system — die stack, interposer, substrate, lid, thermal-interface material, cold plate, optical connector, fiber routing, and airflow or liquid-cooling environment.” Heat can have a bigger impact on an optical signal than on a traditional electric signal, Siemens’ Ferguson said. “This is not necessarily a bad thing, as it means heat can also be used to help in generating the desired signal behavior. Heaters are often inserted into the photonic chips, along with sensors. The sensors detect whether temperature may cause unwanted signal distortions and, if so, provide feedback to the heaters to adjust accordingly.” Axiomise’s Darbari agreed. “In an electronic stack, heat is a performance and reliability problem. In a photonic chiplet, heat is a functional-correctness problem: silicon micro-rings shift roughly 70 to 80 pm/°C, and a recent Advanced Photonics Nexus review notes that modest temperature variation across a WDM array causes enough drift and crosstalk that active thermal control is standard practice. The worst heat source is usually the neighboring compute ASIC, not the photonic die, so CPO architectures need thermal isolation, active stabilization, and sometimes package-level micro-coolers.” Three considerations follow — thermal, electromagnetic, and mechanical domains must be co-simulated because the loop is bidirectional. “Chiplet placement becomes a functional specification parameter, and cooling choice moves up to architecture definition,” Darbari said. “For verification, we can view correctness as an assume-guarantee contract. The package guarantees a temperature envelope. The tuning loop guarantees lock within it. That compensation logic in the EIC is digital, safety-critical, and provable with formal tools today, and it should be, because a corner-case bug in a tuning servo looks identical in the field to a physics failure.” Those same thermal and verification constraints shape the next architectural question, where optical devices should physically sit relative to electrical compute, memory, and control logic.
Optical chips within systems Data rates are driving the need for photonics. The industry is moving to terahertz frequencies; electrical connections can’t be relied on, forcing that transition. “This is why photonics in data centers and AI infrastructure is a critical enabling technology as we deal with those high data rates,” Keysight’s Faché noted. “We’ll do a lot of the signal processing with electrical signals in electrical integrated circuits, but as we start to look at communication between one system and another system, there is a transition from electric to optical, and the transmission is an optical signal. It has lower power consumption, less heat, and, of course, you can manage very high data rates as well, along with the overall bandwidth you need, so it’s an enabling technology. That’s why it gets so much emphasis from all the hyperscalers and that whole ecosystem.” However, because optical waveguides don’t benefit from shrinkage, optical chips tend to be large. So, in many cases, designers will keep this low in the stack. “In addition to the heaters and sensors, logic devices can often be inserted without significant impact on the optical behaviors due to the distances involved,” said Siemens’ Ferguson. “These can convert signals, or even serve as interposers to pass signals from the substrate to upper-level chiplets. Careful consideration is needed for upper-level chiplet placement, as mechanical stresses can also significantly affect optical behavior.” In the near-term, optical lives at the edge of the package. “Co-packaged optics displacing pluggable modules for scale-up and scale-out links — while electrical handles compute and short-reach,” Orthner said. “Over time that boundary moves inward: optical creeps closer to compute, and links that used to be electrical become optical. The endgame is disaggregation, with optical making a rack, or several, behave like one very large system with pooled memory and larger coherent or semi-coherent domains. The constant across all of that is the fabric: a hop might be electrical on-die, electrical die-to-die, or optical off-package, but the system still must present one coherent view. Optical doesn’t replace the fabric; it extends its reach, and the fabrics that win will be the ones designed from the start to scale seamlessly from a single die out across many — because that’s exactly the transition optics forces.” Jensen Huang said it well at Computex 2026: “You use optics wherever you must. You use copper wherever you can.” The pattern is proximity-driven coexistence, not replacement. “NVIDIA’s Rubin platform still uses copper for in-rack NVLink,” Darbari said. “o-packaged optical NVLink arrives around 2028 with Feynman. Intra-package reach stays electrical indefinitely. Package-to-package and rack-scale reach is where the shift to optics is real, and rack-to-rack was always optical. What’s new is that this is no longer a networking decision made after the silicon is designed. Optical proximity to the ASIC is now the dominant lever for power and latency, so compute die, package, and interconnect must be co-designed from the start, and every boundary in that co-design is a contract that should be specified precisely enough to verify.” Architecting optical in
Finally, for chip architects looking to work optical into projects, there are a few places to begin. Darbari recommends starting from the traffic pattern, not the technology. “If your bottleneck is at package reach, look at CPO or NPO chiplets. Rack-to-rack is already optical-native. Treat the interconnect as a standards decision. Architecting against a UCIe electrical-to-optical boundary lets you source the photonic engine as qualified chiplet IP rather than building optics expertise in-house. Then, budget verification and thermal effort as architecture work, not sign-off. Specify the electrical-to-optical boundary as rigorously as any protocol contract — what the engine guarantees, under what thermal conditions, with what error bounds. In our formal verification work on chiplet interfaces, the worst bugs sit at boundaries where two teams each assumed the other had specified the behavior. An electrical-optical boundary crossing company lines is that risk squared. Meanwhile, verify what is verifiable now. The EIC control logic, UCIe interface, and tuning state machines are digital and provable with today’s formal tools. Don’t wait for photonic verification to reach digital-grade maturity. Engage early and shape supplier requirements with the specification discipline of formal verification, years before the tooling makes it easy.” Meanwhile, Orthner says to start at the system level, not the device level. “Model your data flows first — bandwidth, latency, and energy budgets — and identify which links genuinely need to leave the package. Those are your optical candidates. Then, classify the traffic. What’s cache-coherent and ordering-sensitive, what’s bulk streaming? Only after that does it make sense to think about specific photonic components. Treat the interconnect as a first-class design object from day one and let it tell you where optical earns its place. Don’t start by asking, ‘Where do I put optics?’ Start by mapping how data actually moves, then optimize end-to-end throughput so the fabric can feed an optical link at line rate instead of starving it. Software-driven exploration lets you try those tradeoffs in hours — port counts, topology, where the optical I/O attaches. And validate that the interconnect is correct by construction before you commit to a floorplan.” To Bowers, the prospect of silicon photonics being used for every high-capacity switching chip, every high-speed GPU, TPU, or processor, and for high-bandwidth memory is exciting. “Before touching PIC design, nail down why you need optics. Is it bandwidth density at the package edge (die-to-die scale-up), reach beyond the board (rack-scale), or power efficiency at a given data rate? The answer determines which tier you’re building for. And those are very different design problems with different partners and timelines.”
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