Power densities in modern AI accelerators and HPC devices now routinely exceed 1 W/mm². At the same time, 2.5D packages co-integrate high-power accelerator ASICs (e.g., NVIDIA, AMD) with 8–16 High Bandwidth Memory (HBM) stacks (e.g., Micron, Samsung, SK Hynix), pushing system-level thermal behavior to fundamental limits. These components are designed and optimized independently. Their thermal interaction is determined only at integration, through floorplanning on a shared silicon interposer. This creates a critical coupling problem: localized ASIC hotspots conduct laterally into adjacent HBM stacks, elevating junction temperatures beyond safe limits. The result is reduced operating frequency, performance throttling, and accelerated memory degradation. Read
more here. 
Fig.1: Steady-state temperature map across 8 HBM stacks (4 per ASIC) and 2 ASICs at maximum TDP; Tj ≈ 100 °C at HBM. Source: Vinci The post
Full-Fidelity Thermal Simulation at Floorplanning Speed for 2.5D AI Accelerator Packages appeared first on
Semiconductor Engineering.
Source:
https://semiengineering.com/full-fideli ... -packages/