Researchers from Georgia Institute of Technology and Synopsys published a technical paper titled “A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node.” Abstract Excerpt: The paper proposes “a monolithic-3D (M3D) 6T SRAM at the 2nm node” that integrates BEOL IGO pass-gates with an all-silicon nanosheet latch, buried power rails, and Ru interconnects. It also reports that the resulting cell “achieves a 25% footprint reduction” versus a high-performance silicon baseline and reduces write delay by 42.2% at the subarray level. Find the technical paper here. August 2026. Wang, Po-Chuan, Dongwon Jang, Eknath Sarkar, Alexei Svizhenko, Md. Nahid Haque Shazon, Piyush Kumar, Suman Datta, and Azad Naeemi. “A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node.” arXiv, August 2026. https://doi.org/10.48550/arXiv.2608.22741. The post M3D 6T SRAM With BEOL Pass-Gates at 2nm (Georgia Tech, Synopsys) appeared first on Semiconductor Engineering.
Source: https://semiengineering.com/m3d-6t-sram ... -synopsys/