SCT Intel demos first 3D stacked CMOS transistors combined with backside power and direct backside contact

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SCT Intel demos first 3D stacked CMOS transistors combined with backside power and direct backside contact

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At the 69th annual IEEE International Electron Devices Meeting (IEDM 2023) in San Francisco (9–13 December), Intel of Santa Clara, CA, USA showcased first-of-a-kind advances in 3D stacked CMOS (complementary metal oxide semiconductor) transistors combined with backside power and direct backside contacts. The firm also reported on scaling paths for recent R&D breakthroughs for backside power delivery, such as backside contacts, and it was the first to demonstrate successful large-scale 3D monolithic integration of silicon transistors with gallium nitride (GaN) transistors on the same 300mm wafer, rather than on package...

Source: https://www.semiconductor-today.com/new ... 1223.shtml
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