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Key Takeaways:

• Silicon photonics is moving into mainstream AI, data center, and communications systems, but the design flow still needs tighter integration between photonic, electronic, package, thermal, and system-level tools.
• Existing EDA infrastructure can be reused for photonics, but waveguides, optical phase, wavelength, polarization, thermal drift, and compact modeling require specialized simulation and verification methods.
• The biggest unresolved gap is functional verification, because photonic behavior is continuous and physics-dependent rather than discrete, making automation and AI-assisted workflows increasingly important.

Silicon photonics is moving out of specialized research and into mainstream semiconductor design as AI infrastructure, data centers, and communications systems demand faster, lower-power optical interconnects. But as photons move closer to compute engines, traditional EDA flows must stretch beyond electronic signals to verify waveguides, optical-electrical conversion, thermal drift, mechanical stress, and full electro-optical system behavior. As silicon photonics enters volume production across data centers, AI infrastructure, and optical communications applications, designing a photonic integrated circuit is only part of the challenge. Engineers need to confirm its performance within an electro-optical-electrical (EOE) system. Traditional workflows separate these steps, forcing teams to move between design tools for photonic integrated circuits (PICs) and system simulation platforms. “From a physics perspective, first you deal with electrical signals versus photons, and both are governed by the same first-principles physics equations, Maxwell’s equations,” said Niels Fache, senior vice president at Keysight EDA. “You can solve them for different types of applications at different frequencies. So we’re dealing with electrical currents and voltages on the one hand in the electronics world. Then we deal with waves and photons on the optical side. This means the simulation technologies and techniques, such as finite elements and finite difference time domain, are in common. But you apply them to different types of applications, and so there are going to be differences. That’s why we also added deep specialization in those fields, as that was not a logical organic extension of what we were already doing. We could do it at a circuit level. But at a component level, while you might deal with components such as a laser, you don’t have a direct equivalent of that in the electrical domain. That’s a very specialized component, so you deal with waveguides or ring modulators, which are highly specialized optical components. And we deal with the same physics equations, but very different implementations of it when you compare electronics and optics.” Today’s photonic design flow increasingly resembles the electronic IC design flow, but it is not as automated or mature. “Photonic circuits introduce additional challenges because their behavior depends not only on connectivity, but also on geometry, wavelength, etc.,” according to photonics physicist and researcher John Bowers, a board member and advisor to ChipAgents. “The flow typically begins at the system level, where engineers define the required bandwidth, optical power, wavelength plan, modulation format, insertion-loss budget, thermal constraints, and electrical interfaces. They then use circuit-level models to evaluate the overall architecture before committing to physical device geometries.” At the component level, designers develop waveguides, modulators, photodetectors, resonators, couplers, multiplexers, and laser interfaces using electromagnetic and multiphysics solvers. “Different simulation methods are used for different structures, including mode solvers, finite-difference time-domain simulation, eigenmode expansion, and finite-element analysis,” Bowers said. “Because it is impractical to simulate an entire photonic circuit with a full-wave electromagnetic solver, each component is reduced to a compact model. These models capture properties such as loss, phase, wavelength response, reflection, modulation behavior, and manufacturing variation. The compact models are then assembled into a circuit-level simulation, much as transistor models are used in electronic design.” The circuit is then implemented using a photonic process design kit that contains qualified components, material parameters, layout rules, and compact models for a specific foundry process. “Engineers perform schematic capture, component placement, waveguide routing, and electrical interconnect design within a photonic or electronic-photonic design environment,” he continued. “Then, physical verification includes familiar electronic checks such as design-rule checking and layout-versus-schematic verification, but additional photonics-specific checks are required. These may include optical-path continuity, bend-radius constraints, waveguide spacing, phase matching, insertion loss, reflections, thermal crosstalk, polarization behavior, and wavelength alignment.” Electronic-photonic co-design is especially important. “A practical optical-I/O system includes not only the photonic devices, but also modulator drivers, transimpedance amplifiers, clocking circuits, monitoring photodiodes, heaters, control loops, and calibration logic,” Bowers noted. “The photonic die, electronic die, package, laser, thermal system, and fiber interface must therefore be verified together.” Gilles Lamant, distinguished engineer and Virtuoso platform architect at Cadence, agreed there must be integration between electrical and photonic design. “We talk a lot about intelligent system design, or system design, and photonics is integrated in that vision, and that’s going to make a big difference in how we approach photonics. For us, a photonic design is not an end in itself. It’s part of the system, and that’s going to be a little bit contradictory to some of the other approaches you’re going to see, like from people coming out of university or startups, or even some solutions that are focused solely on the PIC, that are trying to expand through the system that goes around it. We are coming at it from a very different perspective. Is our customer saying we need to have photonic ICs in our system? Yes, you need to be good at designing the photonic IC per se, but from the get-go, the photonic IC is part of a bigger set. That’s why, for example, we developed the photonic IC environment on top of the existing electronic platform because it needs to live together with the same designer. It’s not a different platform. It’s based and grounded in the electronic platform. That electronic platform, already by construction and with a lot of what we do today with chiplets, is grounded in having to resolve thermal problems, EM problems, cross-chiplet problems. We just add the extra dimension that one of those chiplets happens to be a photonic one.” Big picture, in a typical workflow – which is not unique to a photonic integrated circuit – the design team starts at a system level, and that could be in an optical channel, and where there are electrical signals in an integrated circuit, electrical is converted to optical, which is transmitted from one board or from one system to another system in a data center, and then you convert optics back into electronics. “Design teams want to look at that as a system and design it at a system level where you work with behavioral models, behavior of the system,” Keysight’s Fache said. “They might look at, say, the eye diagram, the bit error rate of that system, and specify that system and its individual subsystem and high-level components, then go into a more detailed analysis. Then they take the system-level requirements and break them down component by component and design each individual component. This is where they might design an integrated circuit in a GlobalFoundries technology node and use building blocks that are very specific to the technology in which the component will be manufactured. The models built for these components could come from measurements or be simulated. The architect might drill into individual building blocks and perform a physics-based analysis or perform measurements if they’ve had a chance to build these components and use that in a circuit analysis; as they perform that circuit analysis, they may have an updated model for that building block and bring it back into the system level. Typically, they employ a top-down approach from system to circuit to components, where they connect physics and measurements. But it could also be bottom-up. As they build these models, they may want to push that up to the next level, all the way back to the system, and update the model, because it’s always possible that they come up with an initial design, and they may ultimately have requirements that they can’t meet as they go into implementation. For instance, they might find out that a particular component doesn’t meet the requirements that they’ve set up initially, so they need to go back to the system level and understand the implications of that and see if they can make other trade-offs to work with that performance in the context of the whole system.” Understanding the differences between photonics and traditional electrical chips is key. “Unlike the IC space where electrons are passed through wires to active devices, in photonics, photons traverse through waveguides, and with careful consideration for waveguide curvature, photons can also transport through oxide, allowing the ability to separate and pass signals,” explained John Ferguson, product management director for Calibre nmDRC applications at Siemens EDA. “This can all be done quite fast and with significantly less power. There are various EDA tools that can help designers create the appropriate curvatures for their intended optical behavior, though most are still manually driven and not fully automated.” That need for photonics-aware design becomes even more complex once the optical engine is tied to a specific foundry process, packaging strategy, and system architecture. “Much of the workflow of designing electro-optical devices is foundry-specific, so your workflow depends on which foundries you work with and the architecture you have,” said Vishal Chandrasekar, director of product management at silicon supplier Ayar Labs. “The optical engine architecture that we make is an electronics chip hybrid-bonded onto a photonic chip, and then that combination is packaged on a substrate alongside the GPU or the switch.” Ayar Labs designs the electronics chip and the photonic chip, on PDKs determined by the foundry. “The foundry then does the hybrid bonding of that, and then we do backend testing and validation and the like,” Chandrasekar said. “We sell the optical engine, and then the downstream OSAT packages that optical engine onto the substrate, which has the advanced package GPU on it, and that’s how you get the overall GPU substrate with our optical engine on it.” From a verification perspective, if the waveguides have been properly constructed, the optical signal timing can be determined from the waveguide length. “Performing traditional verification like DRC and LVS is still required but historically has its own challenges,” Ferguson said. “These designs rely on waveguides, and in most designs, every waveguide is on the same GDS or OASIS layer, which makes it difficult to distinguish. In particular, the waveguides can act similarly to wires in that they are passing a signal, but they can also act similarly to an active device, generating or modifying a signal. Identifying the kinds of structures that represent a device from those that represent a wire can be challenging. Also, unlike electrons in a wire, photons can pass through one another largely unimpacted. This leads to designs where waveguides cross one another. Here the challenge is how to recognize that these crossings do not actually represent a short-circuit.” For DRC, the issue is that using sign-off standards like GDSII or OASIS means representing a curve is difficult because the curves get rasterized to grid points. “In other words, the DRC tools do not see the curve as intended,” Ferguson noted. “Instead, they see a distorted version, which can appear to have many width and spacing violations. This puts the burden on the design team to decipher which errors are real and which are due to distortion. This is driving the need for new approaches to more accurately capture the intended structure and/or ways to reverse engineer the rasterization to waive the unintended errors generated.” From the perspective of how die-to-die optics affect multi-chiplet and multi-device systems design, Kent Orthner, vice president of products at Baya Systems, noted that photonics design is still a split flow. “Specialized photonic tools handle the optical portion itself, from electromagnetic simulation to waveguide layout and S-parameter extraction, and that gets handed off to electrical and system simulation for the surrounding electronics.” Baya sits at the system-integration layer rather than in photonic device design. “We add the system consequence,” Orthner said. “As optical moves from a discrete component to a die inside the package, the center of gravity shifts from, ‘Does the I/O work?’ to ‘How does data move coherently across optical and electrical domains?’ That integration layer is where the next set of hard problems lives.” Where the flow remains immature is functional verification. “In digital design, we can ask whether a design meets its specification across every reachable state and answer with mathematical proof,” said Ashish Darbari, CEO of Axiomise. “Photonics has nothing equivalent; verification means simulating a handful of operating points, which is validation, not proof. Closing that gap is the biggest opportunity in photonic tooling over the next five years.” Raha Vafaei, lead product marketing manager at Synopsys, observed that within design and verification flows, photonics is moving from standalone PIC design toward a more multi-die, multi-physics system design. “Design teams still need physics-based photonic simulation for their devices, and it’s still very important to get those accurate, compact models and behavioral models to enable circuit and system-level modeling. On the implementation side, it’s still very important to have photonics-aware implementations, DRC, LVS-style verification, and so on, but it’s also becoming very important to have package-aware analysis and system-level kind of validation. If you’ve got physics-accurate multi-physics combined with system-aware modeling and analysis, then you can raise the productivity, and you can make those architectural trade-offs much earlier. Again, this relies on the fact that you can preserve those photonic behavioral model accuracies across the abstraction levels when you go to circuit-system-level modeling, and then you have those system-level analysis and multi-physics analysis coming together. That way, you don’t face late-stage surprises when you’re bringing all the parts together and integrating. You’ve got the photonic chip, you’ve got the electronics chip, you’ve got packaging design. You’ve got the cooling systems. You’ve got power delivery. When it comes together, you don’t want to be thinking, ‘We’ve done these perfectly,’ and then it comes together and it’s not working. So for co-packaged optics, the question is no longer about whether the photonic circuit works. It’s more about whether the assembled full electro-optical system is going to work predictably and at scale. It’s exciting to bring all of that deep expertise on the photonic side, the multi-physics side, connected with the EDA efficiency and reliability, and the system analysis capabilities, so people can move away from isolated design steps toward a more integrated path to designing co-packaged optics and systems like we’re talking about.” In the beginning, the photonic element in the network was a pluggable module, which was an easy way of connecting servers in a rack, or rack-to-rack. “It’s going to near-packaged optics and then co-packaged optics,” said Priyank Shukla, senior director of product management at Synopsys. “The optics now is coming closer to compute, and you need a lot more verification in addition to just the photonic part. It’s electro-optical, and that’s the other piece where we bridge the gap as we move forward.” The final stages of photonics design include statistical analysis across process and temperature corners, package-level optical and thermal simulation, tape-out, fabrication, and post-silicon characterization. “Measured results are then used to improve the component models and foundry PDKs for future designs,” Bowers said. “AI represents an important opportunity to improve the automation of this optical-I/O design flow. Today, engineers often move manually between system simulation, electromagnetic solvers, layout tools, thermal models, verification environments, and test data. Agentic AI platforms will be able to orchestrate these workflows, connecting information that is currently fragmented across different disciplines. In the future, we expect to see a more automated electronic-photonic design environment in which AI agents continuously generate, simulate, verify, diagnose, and optimize the complete optical-I/O system.” Using existing electrical tools to design optical devices
At present, engineering teams are reusing several decades of electronic-design infrastructure, but augmenting it with new models, solvers, design rules, and verification methods that understand the physics of light. “For instance, a standard SPICE simulator models voltages and currents; a photonic simulator must also represent wavelength, optical phase, polarization, propagation loss, reflections, interference, resonances, and often bidirectional signal flow,” Bowers noted. Ferguson agreed the industry is largely trying to leverage the existing infrastructure. “In some cases, design layout can be done with traditional custom layout tools; in other cases, dedicated tools are enabled. Traditional DRC and LVS tools come into play with some additional capabilities to help. There is also exploration of things like parasitic extraction at the waveguide level, and potentially further extension to PERC-style reliability analysis.” Still, while existing electrical design tools are very important and are used, they are not sufficient by themselves. “If you’re trying to design photonics and optical devices and systems, maybe a simple way would be: if you look at electronics, a wire is mainly a connection with parasitics,” Vafaei said. “But in photonics, the equivalent of that wire is usually a waveguide, which is guiding optical light throughout the device. It’s not just a connection; it’s part of the device. Its geometry, its performance, and everything impacts the function of the device- not just the margins on the performance, but the actual function of the device gets affected. That means optics has its own requirements for being modeled. With electrical simulators, you can use compact and behavioral models to do electro-optical co-simulation, but it’s very important that those models are created and validated with specialized photonic simulations.” At the component level, when those models are being created, the specific things needed for optics are captured, like the optical modes, the wavelength response, phase polarization, and process variation. “Then you bring those compact models into your simulators,” Vafaei explained. “Even at the circuit level, it’s important to have photonics-aware circuit simulation, because there are nonlinear effects and complex things that can happen. If you do have specialized photonic circuit simulators, then you have more accuracy and integrity to offer, because Spice and Verilog are simplified behavioral models. The most productive flow is not about forcing photonic tools into electrical tools, but connecting them cohesively so you have photonic-native accuracy from those simulators and the EDA and multi-physics infrastructures coming together. Then, the customers won’t have to choose between the accuracy of the photonics and the efficiency of the EDA, but can get both things in a unified flow that can span the device to the compact modeling to the circuit-level electro-optic co-simulation and implementations all the way with the package and system-level multiphysics analysis and sign-off.” What often happens is that engineering teams stitch together tools that were never designed to talk to each other. “Much of the ‘photonic EDA work’ is building the glue,” Axiomise’s Darbari said. “Electromagnetic solvers such as Lumerical FDTD handle component physics but are too slow for system-level design, so their output is compressed into compact models that a circuit simulator like INTERCONNECT runs quickly. Layout happens in a cockpit like OptoDesigner. Thermal analysis runs alongside optical simulation from early floor-planning, because uncompensated silicon ring resonators drift roughly 70 to 80 picometers per degree Celsius, and a design correct at room temperature can fail under self-heating.” Design-space exploration still happens with scripted sweeps across wavelength, temperature, and process corners. “That is exactly where digital verification stood before formal methods,” he said. “Simulate what you can think of and hope the bug isn’t in the case you didn’t. What we can do today is apply formal rigor to the digital logic surrounding the photonics, such as the calibration state machines and tuning loops in the electronic IC, because a misbehaving tuning loop breaks a link just as surely as bad optics.” Physics-level differences between electrical and optical design
All of this matters at the physics level. As Bowers explained, “At the physics level, the fundamental difference is that conventional silicon electronics controls the movement of electrons, while silicon photonics controls the propagation of electromagnetic waves, photons. Optical design is governed by Maxwell’s equations and by wave behavior. The designer must consider not only optical power, but also wavelength, phase, polarization, refractive index, interference, reflection, scattering, dispersion, and propagation loss.” And because the waveguides are in silicon, manufacturing them requires significant etching. “Unlike the traditional IC environment, photonic design does rely on active elements, and as such does not benefit from shrinkage,” Ferguson said. “This means that photonic chips are often quite large. On the plus side, there can be fewer total elements than a traditional design, for example, little need for vias and stacked metals.” There are other factors to consider, as well. “Digital design controls a two-level system, ON or OFF, 0 or 1,” Darbari noted. “Digital verification exists because that abstraction lets us reason discretely. Optical design has no such abstraction. Light in a waveguide is a continuous field, and everything that matters (phase, amplitude, polarization, wavelength) is analog. A silicon core (n ≈ 3.45) in oxide cladding (n ≈ 1.45) confines light by total internal reflection — a wire, in spirit, except the insulation is doing physics. The consequences are stark. A degree of temperature drift can shift a ring modulator’s resonance out of its WDM slot. A NAND gate stays a NAND gate when the room warms, but a ring can functionally break. And silicon, being indirect-bandgap, has no efficient native light source, so practically every system relies on an external or hybrid-bonded III-V laser.” Therefore, electronic design is about switching discrete charge states. Optical is a continuous, analog regime governed by wavelength and phase, where temperature alone shifts device behavior, and there’s no transistor-style abstraction to hide behind, Baya Systems’ Orthner said. Put simply, digital design abstracts the physics away so the logic can be verified. “Photonic design can’t, because the physics is the logic. That is why the boundary where optical behavior gets wrapped in a digital contract deserves the most rigorous specification we know how to write,” Darbari said. What’s next for photonics design
The next challenge to overcome in photonics design is scaling, Cadence’s Lamant says. “Datacom is pushing hard on bandwidths, and what we’re seeing is that most of the datacom AI applications have a very high radix with lots of channels because they need to replicate the data in different places. One dimension of scaling is how to put more stuff on the face of your device. That’s deep wavelength division multiplexing, and all the different complexities, and that’s not an EDA challenge. From an EDA perspective, photonic chips tended to be handcrafted by loving designers, a little bit like the RF designers 20 years ago. It’s no longer realistic to assume that every bit of a photonic chip will be handcrafted with love, so automation comes in, and AI can help. But there is core automation of photonic design that is required. You’re not hearing too much about photonic placement, photonic routing. All those things are challenging, because it’s not the same as electronic. It literally is not the same as electronic. The size of the photonic design is increasing, and there is absolutely a need for more automation.” What photonics design needs next is not just better point tools, but a more connected flow that can carry accurate models from device physics through circuit, package, and system-level sign-off. As these designs grow larger and more deeply embedded in AI, data center, and co-packaged optics architectures, the challenge shifts from proving that a single photonic component works to ensuring that the full electro-optical system behaves predictably at scale. That is where automation—and eventually agentic AI — may become essential, helping teams stitch together the physics, verification, and multi-physics analysis that photonics demands. Related Article
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