Extending hardware acceleration to formal verification is a powerful idea to extend hardware acceleration to a verification domain that has not got much attention for acceleration. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,… Read More The post Formal Acceleration on FPGA. Innovation in Verification appeared first on SemiWiki.
Source: https://semiwiki.com/eda/371437-formal- ... ification/